Processor using less hardware and instruction conversion apparatus reducing the number of types of instructions

ABSTRACT

A processor which decodes and executes an instruction sequence includes: a state hold unit for holding, when a predetermined instruction is executed, a renewal state for an execution result of the predetermined instruction; an obtaining unit for obtaining an instruction sequence composed of instructions matching instructions assigned to an instruction set of the processor, where the instruction set is assigned first conditional instructions, a first state condition for a first conditional instruction being mutually exclusive with a second state condition for a second conditional instruction which has a same operation code as the first conditional instruction, the instruction set not being assigned the second conditional instruction, and the first state condition and the second state condition specifying either of one state and a plurality of states; a decoding unit for decoding each instruction in the obtained instruction sequence one by one; a judging unit for judging whether the renewal state is included in either of the state and the plurality of states specified by the first state condition in the first conditional instruction, when the decoding unit decodes the first conditional instruction; and an execution unit for executing, only if a judgement result by the judging unit is affirmative, an operation specified by the operation code in the first conditional instruction decoded by the decoding unit.

This application is based on applications Nos. H9-234354 and H10-095645filed in Japan, the content of which is hereby incorporated byreference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a processor and an instructionconversion apparatus, and in particular to a technique for reducing thenumber of types of instructions and the processor hardware scale whenconditional instructions are used.

2. Related Art

In recent years, improvements in performance and processing speed ofappliances using embedded microprocessors have led to an increasingdemand for microprocessors (hereinafter simply referred to as“processors”) with high processing capability.

A basic technique for increasing processing speed is a pipelineprocessing.

In the pipeline processing, the processing of each instruction isdivided into a plurality of processing units (pipeline stages) andpipeline stages for different instructions are executed in parallel sothat processing speed is improved.

The pipeline processing is disturbed, however, (pipeline stalls occur)when executing a branch, reducing the execution performance of thepipelines to below an ideal level. This phenomenon is called a “branchhazard”.

Recent processors use conditional instructions instead of branchinstructions to reduce branch hazards to improve their processingcapabilities. The conditional instructions are, for instance, describedin detail in “The ARM RISC Chip-A Programmer's Guide”, Addison-WeslyPublishing Company Inc.

FIG. 30 shows an instruction sequence including a conventionalconditional transfer instruction. In FIG. 30, each of the legends “r0”,“r1”, and “r2” represents a register. The instruction 3001 is a transferinstruction for transferring the value “1” to the register “r0”. Theinstruction 3002 is a comparison instruction for comparing the values ofthe registers “r1” and “r2” and setting various flags to indicate thecomparison result. The instruction 3003 is a conditional transferinstruction for referring to the flags and, when the values compared bythe instruction 3002 are equal, transferring the value “0” to theregister “r0”.

FIG. 31 shows a list of conventional conditional transfer instructions3101. This list includes six types of conditional transfer instructions3101. The condition 3102 is a sign indicating a condition specified byeach conditional transfer instruction. When the operation objects “a”and “b” are compared by a comparison instruction, the condition is oneof the following cases: “a” and “b” are equal; “a” and “b” are notequal; “a” is greater than “b”; “a” is greater than or equal to “b”; “a”is smaller than “b”; and “a” is smaller than or equal to “b”. Eachconditional transfer instruction is executed when its condition issatisfied.

FIG. 32 shows conventional instructions, such as comparison instructions(CMP instructions), conditional addition instructions for performingaddition when their conditions are satisfied, conditional transferinstructions for performing transfer when their conditions aresatisfied, and conditional branch instructions for performing branchwhen their conditions are satisfied. In these instructions, last twocharacters of the operation code of each instruction in mnemonic codespecify the condition.

The number of types of conditions of each conditional instruction andeach conditional branch instruction shown in FIG. 32 is ten because theconditions shown in FIG. 32 include conditions for data with signs, inaddition to the conditions shown in FIG. 31.

Accordingly, the total number of types of instructions including acomparison instruction, conditional instructions for each of twooperations (conditional transfer instructions and conditional additioninstructions), and conditional branch instructions is thirty-one. Here,if there are A operations of conditional instructions, the total numberis represented as 11+(10×A).

There are also conditional instructions whose number of types isreduced. These conditional instructions are described in detail in“Hitachi Single Chip RISC Microcomputer SH7000/SH7600 Series ProgrammingManual”, Hitachi, Ltd., p57-p58, p69-p70, and p75-p78.

FIG. 33 shows comparison instructions, conditional additioninstructions, and conditional branch instructions where the number ofinstruction types is reduced.

Here, the conditional instructions and the conditional branchinstructions shown in FIG. 33 use only two types of conditions, that is,a conditional flag is set or is reset. Therefore, FIG. 33 shows twotypes of conditional addition instructions, two types of conditionaltransfer instructions, two types of conditional branch instructions, andfive types of comparison instructions for setting or resetting theconditional flag.

Accordingly, the total number of types of instructions includingcomparison instructions, conditional instructions for each of twooperations, and conditional branch instructions is eleven. Here, ifthere are A types of operations of conditional instructions, the totalnumber of types of instructions including comparison instructions,conditional instructions for each operation, and conditional branchinstructions is represented as 7+(2×A).

Processors performing pipeline processing need to use more types ofconditional instructions to reduce branch hazards as much as possible.

However, because each instruction executed by a processor has afixed-length bit pattern, the number of types of instructions which theprocessor can use is limited.

Accordingly, the number of types of conditional instructions which theprocessor can use is limited. As the number of types of instructionsincreases, more hardware is required to decode-instructions, increasingthe cost of the processor.

SUMMARY OF THE INVENTION

In view of the stated problems, the object of the present invention isto provide an instruction conversion apparatus which reduces the numberof types of instructions and a processor whose hardware scale isreduced, when conditional instructions are used.

To achieve the above object, the processor of the present inventionwhich decodes and executes an instruction sequence includes: a statehold unit for holding, when a predetermined instruction is executed, arenewal state for an execution result of the predetermined instruction;an obtaining unit for obtaining an instruction sequence composed ofinstructions matching instructions assigned to an instruction set of theprocessor, where the instruction set is assigned first conditionalinstructions, a first state condition for a first conditionalinstruction being mutually exclusive with a second state condition for asecond conditional instruction which has a same operation code as thefirst conditional instruction, the instruction set not being assignedthe second conditional instruction, and the first state condition andthe second state condition specifying either of one state and aplurality of states; a decoding unit for decoding each instruction inthe obtained instruction sequence one by one; a judging unit for judgingwhether the renewal state is included in either of the state and theplurality of states specified by the first state condition in the firstconditional instruction, when the decoding unit decodes the firstconditional instruction; and an execution unit for executing, only if ajudgement result by the judging unit is affirmative, an operationspecified by the operation code in the first conditional instructiondecoded by the decoding unit.

With the stated construction, the processor of the present inventionuses an instruction set including only conditional instructionsspecifying one out of a pair of exclusive conditions, not includingconditional instructions specifying the other of the pair. Therefore,the number of types of conditional instructions is reduced, incomparison with a conventional processor.

Accordingly, hardware scale of an instruction decoder can be reduced.Also, when the number of types of instructions is limited, the processorof the present invention can be provided with conditional instructionsof more operations. As a result, when the processor of the presentinvention performs pipeline processing, branch hazards can be reduced.

Here, the renewal state may show a relation between magnitudes of twocomparison objects a and b, the relation corresponding to an executionresult of a type of comparison instruction, where execution of a firstconditional instruction is only possible after a comparison instruction,and the instruction set is assigned three types of first conditionalinstructions, the first condition states of the three types of firstconditional instructions being: 1. one out of “a=b” and “a≠b”; 2. oneout of “a≧b” and “a<b”; and 3. one out of “a≦b” and “a>b”.

With the stated construction, the processor of the present inventionuses three types of conditional instructions for each operation, so thatthe number of types of conditional instructions can be reduced by halfof that of a conventional processor.

Therefore, hardware scale of an instruction decoder can be reduced.Also, when the number of types of instructions is limited, the number oftypes of conditional instructions can be increased by twice of that of aconventional processor. Therefore, when the processor of the presentinvention performs pipeline processing, branch hazards can be reduced.

Here, an operation code included in a conditional instruction may be oneof a transfer operation code, an arithmetic operation code, and a logicoperation code.

With the stated construction, the operation of each conditionalinstruction included in the instruction set of the processor of thepresent invention is a transfer operation, an arithmetic operation, anda logic operation.

Therefore, the processor of the present invention can use conditionaltransfer instructions, conditional arithmetic instructions, andconditional logic instructions. Accordingly, when the processor of thepresent invention performs pipeline processing, branch hazards can bereduced.

To achieve the above object, the processor of the present inventionwhich decodes and executes an instruction sequence includes: anobtaining unit for obtaining an instruction sequence composed ofinstructions matching instructions assigned to an instruction set of theprocessor, where the instruction set is assigned at least one firstconditional flag setting instruction, at least one second conditionalflag setting instruction, and at least one conditional executioninstruction, each first conditional flag setting instruction including afirst condition, and each second conditional flag setting instructionincluding a second condition, each first condition being mutuallyexclusive with one of the second, conditions, each conditional executioninstruction including an operation code that is not included in anyother conditional execution instruction in the instruction set; adecoding unit for decoding each instruction in the obtained instructionsequence one by one; a conditional flag for holding a judgement resultas to whether a predetermined condition is satisfied; a judging unit forjudging, when the decoding unit decodes the first conditional flagsetting instruction, whether the first condition in the firstconditional flag setting instruction is satisfied and has theconditional flag hold a judgement result for the first condition and,when the decoding unit decodes the second conditional flag settinginstruction, judges whether the second condition in the secondconditional flag setting instruction is satisfied and has theconditional flag hold a judgement result for the second condition; andan execution unit for executing, only if the decoding unit decodes theconditional execution instruction and the judgement result held by theconditional flag indicates that a condition for the conditionalexecution instruction is satisfied, an operation specified by theoperation code in the conditional execution instruction.

With the stated construction, the processor of the present inventionuses an instruction set including conditional flag setting instructionsand instructions which are executed when their conditions are satisfied,not including instructions which are executed when their conditions arenot satisfied. Therefore, the instruction set includes only one type ofinstruction which is executed when its condition is satisfied for eachoperation.

A conventional processor uses ten types of conditional instructions foreach operation and two types of instructions which are executed whentheir conditions are satisfied. As the number of operations ofinstructions which are executed when their conditions are satisfiedincreases, the processor of the present invention uses less types of theinstructions.

Accordingly, hardware scale and cost of an instruction decoder can bereduced. Also, when the number of types of instructions are limited, theprocessor of the present invention can use conditional instructions formore operations. Therefore, when the processor of the present inventionperforms pipeline processing, branch hazards can be reduced.

Here, each of the first conditional flag setting instruction and thesecond conditional flag setting instruction may specify two comparisonobjects a and b, where the instruction set is assigned three types offirst conditional flag setting instructions and three types of secondconditional flag setting instructions, the first conditions of the firstconditional flag setting instructions being a combination of thefollowing conditions: 1. one out of “a=b” and “a≠b”; 2. one out of “a≧b”and “a<b”; and 3. one out of “a≦b” and “a>b”, the second conditions ofthe second conditional instructions being three mutually exclusiveconditions for the three first conditions.

With the stated construction, the processor of the present inventionuses six types of conditional flag setting instructions and theconditions of these instructions are three pairs of exclusiveconditions. Therefore, without instructions which are executed whentheir conditions are not satisfied, the processor of the presentinvention can perform the same processing as a conventional processor.

Accordingly, the number of types of instructions can be reduced withoutsacrificing the performance of the processor of the present invention.

Here, the instruction set may be further assigned two types of firstconditional flag setting instructions and two types of secondconditional flag setting instructions, the first conditions of the firstconditional flag setting instructions being a combination of thefollowing conditions: 4. one out of “a≧b” and “a<b”; and 5. one out of“a≦b” and “a>b” (where a and b of conditions 4 and 5 are compared withsigns of a and b being taken into account), and the second conditions ofthe second conditional flag setting instructions being mutuallyexclusive with the first conditions.

With the stated construction, the processor of the present inventionuses ten types of conditional flag setting instructions and theconditions of these instructions are five pairs of exclusive conditions.Therefore, without instructions which are executed when their conditionsare not satisfied, the processor of the present invention can performthe same processing as a conventional processor.

Accordingly, the number of types of instructions can be reduced withoutsacrificing the performance of the processor of the present invention.

Here, an operation code included in a conditional execution instructionmay be one of a transfer operation code, an arithmetic operation code, alogic operation code, and a branch operation code.

With the stated construction, the operation of each instruction which isexecuted when its condition is satisfied included in the instruction setof the processor of the present invention is a transfer operation, anarithmetic operation, a logic operation, or a branch operation.

Therefore, the processor of the present invention can use transferinstructions which are executed when their conditions are satisfied,arithmetic instructions which are executed when their conditions aresatisfied, and logic instructions which are executed when, theirconditions are satisfied, and branch instructions which are executedwhen their conditions are satisfied. Accordingly, when the processor ofthe present invention performs pipeline processing, branch hazards canbe reduced.

To achieve the above object, the instruction conversion apparatus of thepresent invention converts instruction sequences not includingconditional instructions into instruction sequences includingconditional instructions, each of the conditional instructions includinga condition and an operation code and having a processor execute anoperation specified by the operation code only if the condition issatisfied, and includes: an obtaining unit for obtaining an instructionsequence which does not include conditional instructions; an instructionsequence detection unit for detecting, out of the obtained instructionsequence, a conversion target instruction sequence which transfersdifferent transfer objects to a same storage resource depending onwhether a predetermined condition is satisfied; a judging unit forjudging whether an instruction set of a specialized processor isassigned a conditional instruction including a same condition as thepredetermined condition; and a conversion unit for converting, when ajudgement result by the judging unit is affirmative, the conversiontarget instruction sequence into an instruction sequence including aconditional instruction including the predetermined condition and forinterchanging, when the judgement result by the judging unit isnegative, the transfer objects of the conversion target instructionsequence and converts the conversion target instruction sequence into aninstruction sequence including a conditional instruction including acondition that is mutually exclusive with the predetermined condition.

With the stated construction, the instruction conversion apparatus ofthe present invention does not generate undecodable conditionalinstructions but decodable conditional instructions for the specializedprocessor.

Therefore, the instruction conversion apparatus of the present inventioncan reduce the number of types of conditional instructions withoutreducing total number of conditional instructions, so that the number offields for including instructions and a code size can be reduced. Also,the number of types of conditional instructions decodable by thespecialized processor can be reduced without sacrificing the performanceof the specialized processor.

Accordingly, hardware scale of an instruction decoder of the specializedprocessor can be reduced. Also, when the number of types of instructionsis limited, the specialized processor can use conditional instructionsfor more operations in comparison with a conventional processor. As aresult, when the specialized processor performs pipeline processing,branch hazards can be reduced.

Here, the instruction set of the specialized processor may be assigned aconditional instruction including a condition that is mutually exclusivewith a condition included in a conditional instruction judged as notassigned to the instruction set by the judging unit, and conditionsincluded in conditional instructions for a same operation assigned tothe instruction set are not mutually exclusive.

With the stated construction, the judging unit of the instructionconversion apparatus of the present invention judges that thespecialized processor uses an instruction set including conditionalinstructions specifying only one out of a pair of exclusive conditions.Therefore, the instruction conversion apparatus of the present inventiondoes not generate conditional instructions specifying the other of thepair of exclusive conditions.

Here, execution of a conditional instruction may be only possible aftera comparison instruction, and the instruction set may be assigned threetypes of conditional instructions for each operation according to arelation between magnitudes of two comparison objects compared by thecomparison instruction, the conditions of the three types of conditionalinstructions being: 1. one out of “a=b” and “a≠b”; 2. one out of “a≧b”and “a<b”; and 3. one out of “a≦b” and “a>b”.

With the stated construction, the judging unit of the instructionconversion apparatus of the present invention judges that thespecialized processor can decode three types of conditional instructionsfor each operation. Therefore, the number of types of conditionalinstructions is reduced by half of six types of conditional instructionsfor a conventional processor.

Here, each of the transfer objects is one of a numerical value, a valueindicated by a different storage resource, an operation result of anumerical value and a value indicated by the different storage resource,an operation result of numerical values, and an operation result ofvalues indicated by the different storage resource.

With the stated construction, the operation specified by a conditionalinstruction is a transfer operation, an arithmetic operation, and alogic operation.

Therefore, the instruction conversion apparatus can generate conditionalinstructions for all of transfer instructions, arithmetic instructions,and logic instructions. Accordingly, when the specialized processorperforms pipeline processing, branch hazards is reduced.

Here, the conversion target instruction sequence may consecutivelyinclude a conditional branch instruction for branching to a nextinstruction but two, a transfer instruction for transferring a transferobject to a storage resource, an unconditional branch instruction forbranching to a next instruction but one, and a transfer instruction fortransferring another transfer object to the storage resource.

With the stated construction, the instruction sequence detection unitdetects this instruction sequence.

To achieve the above object, the instruction conversion apparatus of thepresent invention converts conditional instructions included ininstruction sequences, each of the conditional instructions including acondition and an operation code and having a processor execute anoperation specified by the operation code only if the condition issatisfied, and includes: an obtaining unit for obtaining an instructionsequence including conditional instructions; a conditional instructiondetection unit for detecting a conditional instruction included in theobtained instruction sequence; a first judging unit for judging whetherthe detected conditional instruction is assigned to an instruction setof a specialized processor; a second judging unit for judging, when ajudgement result by the first judging unit is negative, whether theobtained instruction sequence includes a conversion target instructionsequence which transfers different transfer objects to a same storageresource depending on whether a predetermined condition of the detectedconditional instruction is satisfied; and a conversion unit forinterchanging, when a judgement result by the second judging unit isaffirmative, the transfer objects and converts the detected conditionalinstruction into a conditional instruction including a condition that ismutually exclusive with the predetermined condition.

With the stated construction, the instruction conversion apparatus ofthe present invention can converts undecodable conditional instructionsinto decodable conditional instructions for the specialized processor.

Therefore, the instruction conversion apparatus of the present inventioncan reduce the number of types of conditional instructions withoutreducing total number of conditional instructions, so that the number offields for including instructions and a code size can be reduced. Also,the number of types of conditional instructions decodable by thespecialized processor can be reduced without sacrificing the performanceof the specialized processor.

Accordingly, hardware scale of an instruction decoder of the specializedprocessor can be reduced. Also, when the number of types of instructionsis limited, the specialized processor can use conditional instructionsfor more operations. As a result, when the specialized processorperforms pipeline processing, branch hazards can be reduced.

Here, the instruction set of the specialized processor may be assigned aconditional instruction including a condition being mutually exclusivewith a condition included in a conditional instruction judged as notassigned to the instruction set by the first judging unit, andconditions included in conditional instructions for a same operationassigned to the instruction set are not mutually exclusive.

With the stated construction, the first judging unit of the instructionconversion apparatus of the present invention judges that thespecialized processor uses an instruction set including conditionalinstructions specifying only one out of a pair of exclusive conditions.Therefore, the instruction conversion apparatus of the present inventiondoes not generate conditional instructions specifying the other of thepair of exclusive conditions.

Here, the conversion target instruction sequence consecutively mayinclude a comparison instruction for comparing two comparison objects, atransfer instruction for transferring a predetermined transfer object toa predetermined storage resource, and a conditional instruction fortransferring a transfer object that differs from the predeterminedtransfer object to the predetermined storage resource only if apredetermined condition is satisfied.

With the stated construction, the instruction sequence detection unitdetects this instruction sequence.

Here, the conversion unit may include: an inverse conversion unit forconverting, when a judgement result by the second judging unit isnegative, the instruction sequence including the detected conditionalinstruction into an instruction sequence not including the detectedconditional instruction.

With the stated construction, even if a conditional instruction cannotbe decoded by the specialized processor and cannot be converted into aconditional instruction which can be decoded by the specialized process,this conditional instruction is converted into an original instructionsequence.

Therefore, the instruction conversion apparatus of the present inventiongenerates executable instruction sequences for the specializedprocessor.

To achieve the above object, the instruction conversion apparatus of thepresent invention converts an instruction sequence not including aconditional flag setting instruction and a conditional executioninstruction into an instruction sequence including a conditional flagsetting instruction and a conditional execution instruction, eachconditional flag setting instruction including a condition, having aspecialized processor judge whether the condition is satisfied, andhaving a conditional flag hold a judgement result as to whether thecondition is satisfied, each conditional execution instruction includingan operation code and having the specialized processor execute anoperation specified by the operation code only if a condition of theconditional execution instruction is satisfied. The instructionconversion apparatus includes: an obtaining unit for obtaining aninstruction sequence which does not include conditional flag settinginstructions and conditional execution instructions; an instructionsequence detection unit for detecting, out of the obtained instructionsequence, a conversion target instruction sequence which transfersdifferent transfer objects to a same storage resource depending onwhether a predetermined condition is satisfied; and a conversion unitfor converting the conversion target instruction sequence into aninstruction sequence which includes a conditional flag settinginstruction including the predetermined condition and a conditionalexecution instruction including an operation code which specifies anoperation for transferring a transfer object to the storage resourcewhen the predetermined condition is satisfied.

With the stated construction, the instruction conversion apparatus ofthe present invention generates decodable conditional flag settinginstruction and decodable instructions which are executed when theirconditions are satisfied for the specialized processor.

Therefore, the instruction conversion apparatus of the present inventioncan reduce the number of types of conditional instructions withoutreducing total number of conditional instructions, so that the number offields for including instructions and a code size can be reduced. Also,the number of types of conditional instructions decodable by thespecialized processor can be reduced without sacrificing the performanceof the specialized processor.

Accordingly, hardware scale of an instruction decoder of the specializedprocessor can be reduced. Also, when the number of types of instructionsis limited, the specialized processor can use conditional instructionsfor more operations. As a result, when the specialized processorperforms pipeline processing, branch hazards can be reduced.

When the specialized processor uses instructions which are executed whentheir conditions are satisfied for 20 operations, for instance, it isenough to include in an instruction set 30 types of instructionsincluding 10 types of conditional flag setting instruction and 20 typesof instruction which are executed when their conditions are satisfied(one type of the instruction which is executed when its condition issatisfied×20 operations).

Here, a condition of a conditional flag setting instruction which isconvertible by the conversion unit may be mutually exclusive with acondition of another conditional flag setting instruction which isconvertible by the conversion unit.

With the stated construction, during the generation of instructionswhich are executed when their conditions are not satisfied, it is enoughfor the instruction conversion apparatus of the present invention togenerate conditional flag setting instruction specifying exclusiveconditions and instructions which are executed when their conditions aresatisfied. Therefore, the instruction set does not need to includeinstructions which are executed when their conditions are not satisfied.

Accordingly, instructions which are executed when their conditions arenot satisfied can be eliminated without sacrificing the performance ofthe specialized processor.

Here, each conditional flag setting instruction may specify twocomparison objects a and b, where the instruction set is assigned threetypes of first conditional flag setting instructions and three types ofsecond conditional flag setting instructions, the first conditions ofthe first conditional flag setting instructions being a combination ofthe following conditions: 1. one out of “a=b” and “a≠b”; 2. one out of“a≧b” and “a<b”; and 3. one out of “a≦b” and “a>b”, the secondconditions of the second conditional flag setting instructions beingthree mutually exclusive conditions for the three first conditions.

With the stated construction, the conversion unit of the instructionconversion apparatus of the present invention generates six types ofconditional flag setting instruction. Each pair of the conditions ofthese instructions is in an exclusive relation. Therefore, even if aninstruction set does not include instructions which are executed whentheir conditions are not satisfied, the same processing as aconventional processor can be performed.

Accordingly, the number of types of instructions can be reduced withoutsacrificing the performance of the specialized processor.

Here, the conversion target instruction sequence may consecutivelyinclude a comparison instruction for comparing two comparison objects, aconditional branch instruction for branching to a next instruction buttwo when a predetermined condition is satisfied, a transfer instructionfor transferring a predetermined transfer object to a predeterminedstorage resource, an unconditional branch instruction for branching to anext instruction but one, and a transfer instruction for transferring atransfer object that differs from the predetermined transfer object tothe predetermined storage resource.

With the stated construction, the instruction sequence detection unitdetects this instruction sequence.

Here, the conversion target instruction sequence may consecutivelyinclude a comparison instruction for comparing two comparison objects, atransfer instruction for transferring a predetermined transfer object toa predetermined storage resource, and a conditional instruction fortransferring a transfer object that differs from the predeterminedtransfer object to the predetermined storage resource only if apredetermined condition is satisfied.

With the stated construction, the instruction sequence detection unitdetects this instruction sequence.

Here, the conversion target instruction sequence may consecutivelyinclude a comparison instruction for comparing two comparison objects, aconditional instruction for transferring a predetermined transfer objectto a predetermined storage resource only if a predetermined condition isnot satisfied, and a conditional instruction for transferring a transferobject that differs from the predetermined transfer object to thepredetermined storage resource only if the predetermined condition issatisfied.

With the stated construction, the instruction sequence detection unitdetects this instruction sequence.

To achieve the above object, the computer-readable recording medium ofthe present invention records an instruction conversion program forhaving a computer perform a method of converting instruction sequencesnot including conditional instructions into instruction sequencesincluding conditional instructions, each of the conditional instructionsincluding a condition and an operation code and having a processorexecute an operation specified by the operation code only if thecondition is satisfied. The program includes: an obtaining step forobtaining an instruction sequence which does not include conditionalinstructions; an instruction sequence detection step for detecting, outof the obtained instruction sequence, a conversion target instructionsequence which transfers different transfer objects to a same storageresource depending on whether a predetermined condition is satisfied; ajudging step for judging whether an instruction set of a specializedprocessor is assigned a conditional instruction including a samecondition as the predetermined condition; and a conversion step forconverting, when a judgement result in the judging step is affirmative,the conversion target instruction sequence into an instruction sequenceincluding a conditional instruction including the predeterminedcondition and for interchanging, when the judgement result in thejudging step is negative, the transfer objects of the conversion targetinstruction sequence and converts the conversion target instructionsequence into an instruction sequence including a conditionalinstruction including a condition that is mutually exclusive with thepredetermined condition.

With the stated steps, the instruction conversion program of the presentinvention does not generate undecodable conditional instructions butdecodable conditional instructions for the specialized processor.

Therefore, the instruction conversion program of the present inventioncan reduce the number of types of conditional instructions withoutreducing total number of conditional instructions, so that the number offields for including instructions and a code size can be reduced. Also,the number of types of conditional instructions decodable by thespecialized processor can be reduced without sacrificing the performanceof the specialized processor.

Accordingly, hardware scale of an instruction decoder of the specializedprocessor can be reduced. Also, when the number of types of instructionsis limited, the specialized processor can use conditional instructionsfor more operations in comparison with a conventional processor. As aresult, when the specialized processor performs pipeline processing,branch hazards can be reduced.

To achieve the above object, the computer-readable recording medium ofthe present invention records an instruction conversion program forhaving a computer perform a method of converting conditionalinstructions included in instruction sequences, each of the conditionalinstructions including a condition and an operation code and having aprocessor execute an operation specified by the operation code only ifthe condition is satisfied. The program includes: an obtaining step forobtaining an instruction sequence including conditional instructions; aconditional instruction detection step for detecting a conditionalinstruction included in the obtained instruction sequence; a firstjudging step for judging whether the detected conditional instruction isassigned to an instruction set of a specialized processor; a secondjudging step for judging, when a judgement result in the first judgingstep is negative, whether the obtained instruction sequence includes aconversion target instruction sequence which transfers differenttransfer objects to a same storage resource depending on whether apredetermined condition of the detected conditional instruction issatisfied; and a conversion step for interchanging, when a judgementresult in the second judging step is affirmative, the transfer objectsand converts the detected conditional instruction into a conditionalinstruction including a condition that is mutually exclusive with thepredetermined condition.

With the stated steps, the instruction conversion program of the presentinvention can converts undecodable conditional instructions intodecodable conditional instructions for the specialized processor.

Therefore, the instruction conversion program of the present inventioncan reduce the number of types of conditional instructions withoutreducing total number of conditional instructions, so that the number offields for including instructions and a code size can be reduced. Also,the number of types of conditional instructions decodable by thespecialized processor can be reduced without sacrificing the performanceof the specialized processor.

Accordingly, hardware scale of an instruction decoder of the specializedprocessor can be reduced. Also, when the number of types of instructionsis limited, the specialized processor can use conditional instructionsfor more operations. As a result, when the specialized processorperforms pipeline processing, branch hazards can be reduced.

To achieve the above object, the computer-readable recording medium ofthe present invention records an instruction conversion program forhaving a computer perform a method of converting an instruction sequencenot including a conditional flag setting instruction and a conditionalexecution instruction into an instruction sequence including aconditional flag setting instruction and a conditional executioninstruction, each conditional flag setting instruction including acondition, having a specialized processor judge whether the condition issatisfied, and having a conditional flag hold a judgement result as towhether the condition is satisfied, each conditional executioninstruction including an operation code and having the specializedprocessor execute an operation specified by the operation code only if acondition of the conditional execution instruction is satisfied. Theprogram includes: an obtaining step for obtaining an instructionsequence which does not include conditional flag setting instructionsand conditional execution instructions; an instruction sequencedetection step for detecting, out of the obtained instruction sequence,a conversion target instruction sequence which transfers differenttransfer objects to a same storage resource depending on whether apredetermined condition is satisfied; and a conversion step forconverting the conversion target instruction sequence into aninstruction sequence which includes a conditional flag settinginstruction including the predetermined condition and a conditionalexecution instruction including an operation code which specifies anoperation for transferring a transfer object to the storage resourcewhen the predetermined condition is satisfied.

With the stated steps, the instruction conversion program of the presentinvention generates decodable conditional flag setting instruction anddecodable instructions which are executed when their conditions aresatisfied for the specialized processor.

Therefore, the instruction conversion program of the present inventioncan reduce the number of types of conditional instructions withoutreducing total number of conditional instructions, so that the number offields for including instructions and a code size can be reduced. Also,the number of types of conditional instructions decodable by thespecialized processor can be reduced without sacrificing the performanceof the specialized processor.

Accordingly, hardware scale of an instruction decoder of the specializedprocessor can be reduced. Also, when the number of types of instructionsis limited, the specialized processor can use conditional instructionsfor more operations. As a result, when the specialized processorperforms pipeline processing, branch hazards can be reduced.

When the specialized processor uses instructions which are executed whentheir conditions are satisfied for 20 operations, for instance, it isenough to include in an instruction set 30 types of instructionsincluding 10 types of conditional flag setting instruction and 20 typesof instruction which are executed when their conditions are satisfied(one type of the instruction which is executed when its condition issatisfied×20 operations).

As described above, the present invention has great practical uses.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects, advantages and features of the invention willbecome apparent from the following description thereof taken inconjunction with the accompanying drawings which illustrate a specificembodiment of the invention. In the drawings:

FIG. 1 shows a construction of the processor of the present inventionwhich executes machine instructions generated by the compiler of thepresent invention;

FIG. 2 shows a list of example conditional transfer instructions whichthe processor Embodiment 1 can execute;

FIG. 3 is a flowchart showing the operation of the compiler ofEmbodiment 1;

FIGS. 4A and 4B show examples of C source programs written in Clanguage;

FIGS. 5A and 5B show intermediate code sequences which do not includeconditional transfer instructions and are respectively generated fromthe C source programs shown in FIGS. 4A and 4B;

FIGS. 6A and 6B show intermediate code sequences which includeconditional transfer instructions and are respectively generated fromthe intermediate code sequence shown in FIGS. 5A and 5B;

FIGS. 7A and 7B show machine instruction sequences respectivelygenerated from the intermediate code sequences shown in FIGS. 6A and 6B;

FIG. 8 is a flowchart showing the operation of the compiler ofEmbodiment 2;

FIG. 9 shows an intermediate code sequence including a conditionaltransfer instruction generated from the C source program shown in FIG.4B;

FIG. 10 shows a list of example conditional branch instructions whichthe processor of Embodiment 3 can execute;

FIG. 11 is a flowchart showing the operation of the compiler ofEmbodiment 3;

FIG. 12 shows an intermediate code sequence which the processor ofEmbodiment 3 can decode and is generated from the intermediate codesequence shown in FIG. 5B which the process of Embodiment 3 cannotdecode;

FIG. 13 shows a machine instruction sequence generated from theintermediate code sequence shown in FIG. 12;

FIG. 14 shows comparison instructions, a conditional additioninstruction, a conditional transfer instruction, and a conditionalbranch instruction of Embodiment 4, where the number of types ofinstructions is reduced;

FIG. 15 shows the construction of the compiler of Embodiment 4;

FIG. 16 shows an example of the C source code 1511 which is written in Clanguage and is input into the compiler of Embodiment 4;

FIG. 17 shows the first intermediate code 1512;

FIG. 18 shows the second intermediate code 1513;

FIG. 19 shows the machine instruction 1515;

FIG. 20 is a flowchart showing the operation of the object codedetection means 1502 and the conditional instruction conversion means1503 of Embodiment 4;

FIG. 21 shows the first intermediate code 1512;

FIG. 22 is a flowchart showing the operation of the object codedetection means 1502 and the conditional instruction conversion means1503 of Embodiment 5;

FIG. 23 shows the first intermediate code 1512;

FIG. 24 is a flowchart showing the operation of the object codedetection means 1502 and the conditional instruction conversion means1503 of Embodiment 6;

FIG. 25 shows a list of example conditional addition instructions whichthe processor of Embodiment 1 can execute;

FIG. 26 shows an example of a C source program written in C language;

FIG. 27 shows an intermediate code sequence which does not includeconditional addition instructions and is generated from the C sourceprogram shown in FIG. 26;

FIG. 28 shows an intermediate code sequence which includes a conditionaladdition instruction and is generated from the intermediate codesequence shown in FIG. 27;

FIG. 29 shows a machine instruction sequence generated from theintermediate code sequence shown in FIG. 28;

FIG. 30 shows an instruction sequence including a conventionalconditional transfer instruction;

FIG. 31 shows a list of conventional transfer instructions;

FIG. 32 shows a conventional comparison instruction (CMP instruction),conditional addition instructions which are executed when theirconditions are satisfied, conditional transfer instructions which areexecuted when their conditions are satisfied, and conditional branchinstructions which are executed when their conditions are satisfied; and

FIG. 33 shows comparison instructions, conditional additioninstructions, conditional transfer instructions, and conditional branchinstructions, where the number of types of instructions is reduced.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 shows the construction of the processor of the present inventionwhich executes machine instructions generated by the compiler of thepresent invention.

This processor includes the operation flag hold means 101, instructiondecoding means 102, the instruction execution means 103, and theinstruction execution halt means 104.

The operation flag hold means 101 holds an operation flag showing aninstruction execution state, and outputs the operation flag state signal111 showing the instruction execution state.

The instruction decoding means 102 decodes machine instructions andoutputs the instruction execution means control signal 112. Whendecoding conditional instructions, the instruction decoding means 102outputs the conditional instruction designation signal 113.

The instruction execution means 103 executes instructions according tothe instruction execution means control signal output from theinstruction decoding means 102.

The instruction execution halt means 104 receives the operation flagstate signal 111 output from the operation flag hold means 101 and theconditional instruction designation signal 113 output from theinstruction decoding means 102. When a condition is not satisfied, theinstruction execution halt means 104 outputs the instruction executionhalt signal 113 to the instruction execution means 103 so that theinstruction execution means 103 halts its instruction execution.

It should be noted here that in this processor, the instructionexecution halt means 104 may be replaced by an instruction executioncontinuation means and, when a condition is satisfied, the instructionexecution continuation means may output an instruction execution signalto the instruction execution means 103 so that the instruction executionmeans 103 executes instructions. The processor including the instructionexecution halt means 104 and the processor including the instructionexecution continuation means are effectively the same, only with inverselogic.

Embodiment 1

Among the six conditional transfer instructions shown in FIG. 31, theprocessor of Embodiment 1 decodes and executes conditional transferinstructions specifying one out of a pair of conditions in an exclusiverelation and does not decode and execute conditional transferinstructions specifying the other of the pair of conditions. Here,examples of conditions in an exclusive relation are “a=b” and “a≠b”, and“a>b” and “a≦b”.

More specifically, when two operation objects “a” and “b” are comparedby a comparison instruction, the present processor decodes and executesa conditional instruction specifying one out of a pair of conditionsthat are “a” and “b” are equal and “a” and “b” are not equal.

Similarly, the present processor decodes and executes a conditionalinstruction specifying one out of a pair of conditions that are ‘“a” isgreater than “b”’ and ‘“a” is equal to or smaller than “b”’, and decodesand executes a conditional instruction specifying one out of a pair ofconditions that are ‘“a” is smaller than “b”’ and ‘“a” is equal to orgreater than “b”’.

FIG. 2 shows a list of conditional transfer instructions which thepresent processor can execute. This list includes three types ofconditional transfer instructions 201. Each of the conditions 202 is asign indicating the condition specified by one conditional transferinstruction. When two operation objects “a” and “b” are compared by acomparison instruction, the condition of the instruction “moveq” 203 isthat “a” and “b” are equal; the condition of the instruction “movgt” 204is that “a” is greater than “b”; and the condition of the instruction“movge” 205 is that “a” is equal to or greater than “b”. Each of theseconditional transfer instructions executes transfer when its conditionis satisfied.

The present compiler generates only the conditional transferinstructions shown in FIG. 2, out of the conditional transferinstructions shown in FIG. 31.

FIG. 3 is a flowchart showing the operation of the compiler ofEmbodiment 1.

FIGS. 4A and 4B show example C source programs which are written in Clanguage and are input into the present compiler.

With the C source program shown in FIG. 4A, the variable “a” and thevariable “b” are compared and, when they are equal, “1” is assigned tothe variable “c”; when they are not equal, “0” is assigned to thevariable “c” and the function “f” is called.

With the C source program shown in FIG. 4B, the variable “a” and thevariable “b” are compared and, when they are not equal, “1” is assignedto the variable “c”; when they are equal, “0” is assigned to thevariable “c” and the function “f” is called.

FIGS. 5A and 5B show intermediate code sequences which do not includeconditional transfer instructions and are respectively generated fromthe C source programs shown in FIG. 4A and 4B in step S301 of theflowchart shown in FIG. 3. Note that FIGS. 5A and 5B show the sameintermediate code sequences as those generated by a conventionalcompiler during the conversion of the C source programs shown in FIGS.4A and 4B into machine instructions.

In FIG. 5A, the intermediate code 501 is a code for comparing thevariables “a” and “b” and setting a flag to indicate the comparisonresult; the intermediate code 502 is a code for branching to the label“Lt” 507 when the variables “a” and “b” are equal; the intermediate code503 is a code for transferring the immediate “0” to the variable “c”;the intermediate code 504 is a code for branching to the label “L” 508;the intermediate code 505 is a code for transferring the immediate “1”to the variable “c”; and the intermediate code 506 is a code for callingthe function “f”.

In FIG. 5B, the intermediate code 511 is a code for comparing thevariables “a” and “b” and setting a flag to indicate the comparisonresult; the intermediate code 512 is a code for branching to the label“Lt” 517 when the variables “a” and “b” are not equal; the intermediatecode 513 is a code for transferring the immediate “0” to the variable“c”; the intermediate code 514 is a code for branching to the label “L”518; the intermediate code 515 is a code for transferring the immediate“1” to the variable “c”; and the intermediate code 516 is a code forcalling the function “f”.

FIGS. 6A and 6B show intermediate code sequences including conditionaltransfer instructions. These intermediate code sequences arerespectively generated by the present compiler from the intermediatecode sequences not including conditional transfer instructions shown inFIGS. 5A and 5B in steps S302-S118 of the flowchart shown in FIG. 3.

In FIG. 6A, the intermediate code 601 is a code for comparing thevariables “a” and “b” and setting a flag to indicate the comparisonresult; the intermediate code 602 is a code for transferring theimmediate “0” to the variable “c”; the intermediate code 603 is a codefor transferring the immediate “1” to the variable “c” when thevariables “a” and “b” are equal; and the intermediate code 604 is a codefor calling the function “f”.

In FIG. 6B, the intermediate code 611 is a code for comparing thevariables “a” and “b” and setting a flag to indicate the comparisonresult; the intermediate code 612 is a code for transferring theimmediate “1” to the variable “c”; the intermediate code 613 is a codefor transferring the immediate “0” to the variable “c” when thevariables “a” and “b” are equal; and the intermediate code 614 is a codefor calling the function “f”.

FIGS. 7A and 7B show machine instruction sequences. The machineinstruction sequences are respectively generated by the present compilerfrom the intermediate code sequences including conditional transferinstructions shown in FIGS. 6A and 6B in step S319 of the flowchartshown in FIG. 3. Note that the machine instruction sequences shown inFIGS. 7A and 7B are respectively the same as those generated fromintermediate code sequences including conditional transfer instructionsshown in FIGS. 6A and 6B.

In FIG. 7A, the machine instruction 701 is an instruction for comparingthe values of registers “r0” and “r1” and setting a flag to indicate thecomparison result; the machine instruction 702 is an instruction fortransferring the immediate “0” to the register “r2”; the machineinstruction 703 is an instruction for transferring the immediate “1” tothe register “r2” when the values of the registers “r0” and “r1” areequal; and the machine instruction 704 is an instruction for calling thefunction “f”.

In FIG. 7B, the machine instruction 711 is an instruction for comparingthe values of registers “r0” and “r1” and setting a flag to indicate thecomparison result; the machine instruction 712 is an instruction fortransferring the immediate “1” to the register “r2”; the machineinstruction 713 is an instruction for transferring the immediate “0” tothe register “r2” when the values of the registers “r0” and “r1” areequal; and the machine instruction 714 is an instruction for calling thefunction “f”.

The following is a description of the process in the case where the Csource program shown in FIG. 4A is input into the present compiler, withreference to FIG. 3.

(1a) The input C source program is converted into an intermediate codesequence without a conditional transfer instruction and the initialvalue “1” is assigned to the variable n (step S301). In this example,the C source program shown in FIG. 4A is converted into the intermediatecode sequence shown in FIG. 5A.

(2a) The compiler judges whether the n^(th) intermediate code is anintermediate code indicating a conditional branch whose branchdestination is the n+3^(th) code (step S302) This process is repeated byincrementing n by one until the judgement result becomes Yes (in thisrepetition, the judgement result in step S302 is No, the processproceeds to step S314, and the result in step S318 is Yes). In thisexample, the intermediate code 502 shown in FIG. 5A indicates aconditional branch whose branch destination is the n+3^(th) code, sothat the judgement result in step S302 becomes Yes when n is 2 and theprocess proceeds to the judgement in step S303.

(3a) The compiler judges whether the n+1^(th) intermediate codeindicates a transfer (step S303). When the judgement result is No, n isincremented by one and the process returns to step S302 to find anintermediate code indicating a conditional branch (in this case, thejudgement result in step S303 is No, the process proceeds to step S314,and the judgement result in step S318 is Yes). In this example, theintermediate code 503 shown in FIG. 5A is an intermediate codeindicating a transfer, so that the judgement result in step S303 becomesYes when n+1 is 3 and the process proceeds to step S304.

(4a) The compiler judges whether the n+2^(th) intermediate code is anintermediate code indicating an unconditional branch whose branchdestination is the n+4^(th) code (step S304). When the judgement resultis No, n is incremented by 2 and the process returns to step S302 tofind an intermediate code indicating a conditional branch (in this case,the judgement result in step S304 is No, the process proceeds to stepS315, and the judgement result in step S318 is Yes). In this example,the intermediate code 504 shown in FIG. 5A indicates an unconditionalbranch whose branch destination is the n+4^(th) code so that, when n+2is 4, the judgement result in step S304 becomes Yes and the processproceeds to step S304.

(5a) The compiler judges whether the n+3^(th) intermediate code and then+1^(th) intermediate code indicate transfers to the same variable (stepS305). When the judgement result is No, n is incremented by 3 and theprocess returns to step S302 to find an intermediate code indicating aconditional branch (in this case, the judgement result in step S305 isNo, the process proceeds to step S316, and the judgement result in stepS318 is Yes). In this example, the intermediate code 505 shown in FIG.5A indicates a transfer to the same variable as the intermediate code503. Therefore, when n+3 is 5, the judgement result in step S305 becomesYes and the process proceeds to step S306.

(6a) The compiler judges whether the present processor can execute aconditional transfer instruction specifying the same condition as thatspecified by the n^(th) intermediate code indicating a conditionalbranch (step S306). In this example, the condition specified by theintermediate code 502 indicating a conditional branch shown in FIG. 5Ais that “a” and “b” are equal. As shown in FIG. 2, the present processorcan execute a conditional transfer instruction specifying the samecondition, so that the judgement result becomes Yes and the processproceeds to the conversion process in step S307.

(7a) The nth intermediate code indicating a conditional branch isdeleted (step S307).

(8a) The n+2^(th) intermediate code indicating an unconditional branchis deleted (step S308).

(9a) The n+3^(th) intermediate code indicating a transfer is convertedinto a conditional transfer instruction specifying the same condition asthat specified by the n^(th) intermediate code indicating a conditionalbranch (step S309).

(10a) N is incremented by 4 and the compiler judges whether there is anyother intermediate code to be processed (steps S317 and S318). If so,the process in steps S302-318 is repeated. In this example, theintermediate code sequence including a conditional transfer instructionshown in FIG. 6A is generated.

(11a) An intermediate code sequence including conditional transferinstructions is inverted into a machine instruction sequence (stepS319). In this example, the intermediate code sequence shown in FIG. 6Ais converted into the machine instruction sequence shown in FIG. 7A.

The following description concerns the process in the case where the Csource program shown in FIG. 4B is input into the present compiler.

(1b) In step S301, the C source program shown in FIG. 4B is convertedinto the intermediate code sequence shown in FIG. 5B.

(2b) The intermediate code 512 shown in FIG. 5B indicates a conditionalbranch whose branch destination is the n+3^(th) intermediate code.Therefore, when n is 2, the judgement result in step S302 becomes Yesand the process proceeds to step S303.

(3b) The intermediate code 513 shown in FIG. 5B indicates a transfer sothat, when n+1 is 3, the judgement result in step S303 becomes Yes andthe process proceeds to the judgement in step S304.

(4b) The intermediate code 514 shown in FIG. 5B indicates anunconditional branch whose branch destination is the n+4^(th)intermediate code. Therefore, when n+2 is 4, the judgement result instep S304 becomes Yes and the process proceeds to the judgement in stepS304.

(5b) The intermediate code 515 shown in FIG. 5B indicates a transfer tothe same variable as intermediate code 513. Therefore, when n+3 is 5,the judgement result in step S305 becomes Yes and the process proceedsto step S306.

(6b) The condition specified by the intermediate code 512 indicating aconditional branch shown in FIG. 5B is that “a” and “b” are not equal.As shown in FIG. 5B, the present processor cannot execute a conditionaltransfer instruction specifying the same condition, so that thejudgement result in step S306 is No and the process proceeds to theconversion process in step S310.

(7b) The nth intermediate code indicating a conditional branch isdeleted (step S310).

(8b) The n+2 intermediate code indicating an unconditional branch isdeleted (step S311).

(9b) The n+1^(th) intermediate code indicating a transfer is convertedinto a conditional transfer instruction specifying an exclusivecondition for the condition specified by the n^(th) intermediate codeindicating a conditional branch (step S312).

(10b) The n+3^(th) transfer code and the n+1^(th) transfer code areinterchanged.

(11b) N is incremented by 4 and the compiler judges whether there is anyother intermediate code to be processed (steps S317 and S318). If so,the process in steps S302-318 is repeated. In this example, theintermediate code sequence including a conditional transfer instructionshown in FIG. 6B is generated.

(12b) In step S319, the intermediate code sequence shown in FIG. 6B isconverted into the machine instruction sequence shown in FIG. 7B.

In this manner, the present compiler generates only conditional transferinstructions which the present processor can execute.

Embodiment 2

FIG. 8 is a flowchart showing the operation of the compiler of thepresent embodiment.

FIG. 9 shows an intermediate code sequence including a conditionaltransfer instruction. This intermediate code sequence is generated bythe present compiler from the C source program shown in FIG. 4B in stepS801 of the flowchart shown in FIG. 8. Note that FIG. 9 shows the sameintermediate code sequence as that generated by a conventional compilerfor generating conditional transfer instruction during the conversion ofthe C source program shown in FIG. 4B into machine instructions.

In FIG. 9, the intermediate code 901 is a code for comparing thevariables “a” and “b” and setting a flag to indicate the comparisonresult; the intermediate code 902 is a code for transferring theimmediate “0” to the variable “c”; the intermediate code 903 is a codefor transferring the immediate “1” to the variable “c” when thevariables “a” and “b” are not equal; and the intermediate code 904 is acode for calling the function “f”.

Here, the processor of the present embodiment can execute theconditional transfer instructions shown in FIG. 2, as the processor ofEmbodiment 1.

The following description concerns the process in the case where the Csource program shown in FIG. 4B is input into the present processor,with reference to figures such as FIG. 8.

It should be noted here that each step shown in FIG. 8 that has the samenumber as a step in. FIG. 3 executes the same process as before.

(1) The input C source program is converted into an intermediate codesequence including a conditional transfer instruction, and the initialvalue “1” is assigned to the variable n (step S801). In this example,the C source program shown in FIG. 4B is converted into the intermediatecode sequence shown in FIG. 9.

(2) The compiler judges whether the n^(th) intermediate code indicates aconditional transfer (step S802). This process is repeated byincrementing n by one until the judgement result becomes “Yes” (in thisrepetition, the judgement result in step S802 is No, the processproceeds to step S807, and the judgement result in step S808 is Yes). Inthis example, the intermediate code 903 shown in FIG. 9 indicates aconditional transfer, so that the judgement result in step S802 becomesYes when n is 3 and the process proceeds to the judgement in step S803.

(3) The compiler judges whether the present processor can execute then^(th) conditional transfer code (step S803) Here, the conditionspecified by the intermediate code 903 indicating a conditional transferis that “a” and “b” are not equal. As shown in FIG. 2, the presentprocessor cannot execute a conditional branch instruction specifyingthis condition. Therefore, the judgement result in this step is No andthe process proceeds to the judgement in step S804.

(4) The compiler judges whether the n−2th intermediate code indicates acomparison (step S804). When the judgement result is No, the processproceeds to the inverse conversion process in step S810; when Yes, theprocess proceeds to the judgement in step S805. In this example, theintermediate code 901 shown in FIG. 9 indicates a comparison, so thatwhen n−2 is 1, the judgement result in step S804 becomes Yes and theprocess proceeds to step S805.

(5) The compiler judges whether the n−1th intermediate code indicates atransfer to the same variable as the n^(th) intermediate code indicatinga conditional transfer (step S805). When the judgement result is No, theprocess proceeds to the deletion process of conditional transferinstructions in step S810; when Yes, the process proceeds to theconversion process in step S805. In this example, the intermediate code902 shown in FIG. 9 indicates a transfer to the same variable as theintermediate code 903 indicating a conditional transfer. Therefore, whenn−1 is 3, the judgement result in step S805 becomes Yes and the,process-proceeds to the conversion process in step S806.

(6) The condition of the n^(th) intermediate code indicating aconditional transfer is changed to an exclusive condition and thetransfer values of the n−1th and n^(th) intermediate codes areinterchanged (step S806). In this example, the condition specified bythe intermediate code 903 indicating a conditional branch shown in FIG.9, that is “a” and “b” are not equal (≠), is changed to an exclusivecondition (equal =). That is, “c=:ne 1” is changed to “c=: eq 1”.

(7) N is incremented by 1 and the compiler judges whether there is anyother intermediate instruction to be processed (steps S807 and S808). Ifso, the process in steps S802-S808 is repeated. In this example, theintermediate code sequence including a conditional transfer instructionshown in FIG. 6B is generated.

(8) In step S319, the intermediate code sequence shown in FIG. 6B isconverted into the machine instruction sequence shown in FIG. 7B.

(9) Each conditional transfer instruction which cannot be executed bythe present processor and also cannot be converted in the conversionprocess in step S806 is inversely converted to an original intermediatecode (step S810). In this example, this process is not performed.

As described above, the present compiler converts unexecutableconditional transfer instructions into executable conditional transferinstructions for the present processor.

Embodiment 3

The processor of the present embodiment decodes and executes onlyconditional branch instructions specifying one out of a pair ofconditions in an exclusive relation, out of the six types of conditionalbranch instructions specifying the same conditions as those specified bythe six types of conditional transfer instructions 3101 shown in FIG.31.

FIG. 10 shows a list of example conditional branch instructions whichthe present processor can execute. This list includes three types ofconditional branch instructions 1001. Each of the conditions 1002 is asign indicating a condition specified by one conditional branchinstruction. When two operation objects “a” and “b” are compared by acomparison instruction, the condition of the “beq” 1003 is that “a” and“b” are equal; that of the “bgt” 1004 is that “a” is greater than “b”;and that of the “bge” 1005 is that “a” is greater than or equal to “b”.Each conditional branch instruction indicates a branch which isperformed when its condition is satisfied. Note that in this embodiment,the present processor cannot execute other conditional instructions.

FIG. 11 is a flowchart showing the operation of the compiler ofEmbodiment 3.

FIG. 12 shows an intermediate code sequence which the present processorcan decode. This intermediate code sequence is generated by the presentcompiler from the intermediate code sequence shown in FIG. 5B, which thepresent processor cannot decode, in steps S302-318 of the flowchartshown in FIG. 11.

In FIG. 12, the intermediate code 1201 is a code for comparing thevariables “a” and “b” and setting a flag to indicate the comparisonresult; the intermediate code 1202 is a code for branching to the label“Lt” 1207 when the variables “a” and “b” are equal; the intermediatecode 1203 is a code for transferring the immediate “1” to the variable“c”; the intermediate code 1204 is a code for branching to the label “L”1208; the intermediate code 1205 is a code for transferring theimmediate “0” to the variable “c”; and the intermediate code 1206 is acode for calling the function “f”.

FIG. 13 shows a machine instruction sequence. This machine instructionsequence is generated by the present compiler from the intermediate codesequence shown in FIG. 12 which the present processor can decode in stepS319 of the flowchart shown in FIG. 11. Note that FIG. 13 shows the samemachine instruction sequence as that generated by a conventionalcompiler from the intermediate code sequence shown in FIG. 12.

In FIG. 13, the machine instruction 1301 is an instruction for comparingvalues of the registers “r0” and “r1” and setting a flag to indicate thecomparison result; the machine instruction 1302 is an instruction forbranching to the label “Lt” 1307 when the values of the registers “r0”and “r1” are equal; the machine instruction 1303 is an instruction fortransferring the immediate “1” to the register “r2”; the machineinstruction 1304 is an instruction for branching to the label “L” 1308;the machine instruction 1305 is an instruction for transferring theimmediate “0” to the register “r2”; and the machine instruction 1306 isan instruction for calling the function “f”.

The following is a description of the processing of the present compilerto which the C source program shown in FIG. 4B is input, with referenceto FIG. 11.

Note that each step shown in FIG. 11 that has the same number as a stepin FIG. 13 executes the same processing as before.

(1) In step S301, the C source program shown in FIG. 4B is convertedinto the intermediate code sequence shown in FIG. 5B.

(2) The intermediate code 512 shown in FIG. 5B indicates a conditionalbranch whose branch destination is the n+3 ^(th) intermediate code.Therefore, when n is 2, the judgement result in step S302 becomes Yesand the process proceeds to step S303.

(3) The intermediate code 513 shown in FIG. 5B indicates a transfer sothat, when n+1 is 3, the judgement result in step S303 becomes Yes andthe process proceeds to the judgement in step S304.

(4) The intermediate code 514 shown in FIG. 5B indicates anunconditional branch whose branch destination is the n+4^(th)intermediate code. Therefore, when n+2 is 4, the judgement result instep S304 becomes Yes and the process proceeds to the judgement in stepS304.

(5) The intermediate code 515 shown in FIG. 5B indicates a transfer tothe same variable as intermediate code 513. Therefore, when n+3 is 5,the judgement result in step S305 becomes Yes and the process proceedsto step S306.

(6) The compiler judges whether the present processor can execute aconditional branch instruction of the same condition as that specifiedby the n^(th) intermediate code indicating a conditional branch. Whenthe judgement result is Yes, the conversion processing is not performed;when No, the process proceeds to the conversion processing (step S1101).In this example, the condition specified by the intermediate code 512indicating a conditional branch shown in FIG. 5B is that “a” and “b” arenot equal. As can be seen from FIG. 10, the present processor cannotexecute a conditional branch instruction specifying this condition, sothat the judgement result becomes No and the process proceeds to theconversion processing in step S1102.

(7) The condition specified by the n^(th) intermediate code indicating aconditional branch is changed into an exclusive condition (step S1102).In this example, the condition specified by the intermediate code 512indicating a conditional branch, that is “a” and “b” are not equal (≠),is changed into an exclusive condition, that is “a” and “b” are equal(=). More specifically, “bne” is changed into “beq”.

(8) The n+3^(th) transfer code and the n+1^(th) transfer code areinterchanged (step S1103). In this example, the fifth transfer code“c=0” and the third transfer code “c=1” are interchanged.

(9) In steps S317 and S318, the present compiler generates theexecutable intermediate code sequence shown in FIG. 12 for the presentprocessor.

(10) In step S319, the present compiler converts the intermediate codesequence shown in FIG. 12 into the machine instruction sequence shown inFIG. 13.

As described above, the present compiler converts unexecutableconditional branch instructions into executable conditional branchinstructions for the present processor.

Embodiment 4

FIG. 14 shows comparison instructions, a conditional additioninstruction, a conditional transfer instruction, and a conditionalbranch instruction, where the number of types of instructions has beenreduced. These instructions are used in the present embodiment.

In FIG. 14, each of the conditional instructions and the conditionalbranch instruction uses only one condition where a conditional flag isset. Therefore, FIG. 14 shows one type of conditional additioninstruction, one type of conditional transfer instruction, one type ofconditional branch instruction, and ten types of comparison instructionsfor setting and resetting the conditional flag.

Therefore, the total number of instructions including the comparisoninstructions, the conditional instructions for two operations, and theconditional branch instruction is thirteen. Here, if the number of typesof operations of conditional instructions is assumed to be A, the totalnumber of types of instructions including comparison instructions,conditional instructions for each operation, and the conditional branchinstruction is represented as 11+A.

Here, each total number of types of instructions including comparisoninstructions, conditional addition instructions, conditional transferinstructions, and conditional branch instructions in FIGS. 14, 32, and33 is compared. When the number of types of conditional instructions Ais 0-3, the total number of instruction types shown in FIG. 33 is thelowest. When the number of types of conditional instructions A is 4, thetotal number of instruction types shown in FIGS. 14 and 33 is fifteen,which is the lowest (in this case, the total number of instruction typesshown in FIG. 32 is 51). When the total number of types of conditionalinstructions A is 5 or more, the total number of instruction types shownin FIG. 14 is the lowest. As A increases, the difference between thesefigures widens.

The processor of the present embodiment decodes and executes thecomparison instructions, the conditional addition instruction, theconditional transfer instruction, and the conditional branch instructionshown in FIG. 14.

FIG. 15 shows the construction of the present compiler.

The present compiler includes the intermediate code generation means1501, the object code detection means 1502, the conditional instructionconversion means 1503, the intermediate code optimization means 1504,and the machine instruction generation means 1505.

FIG. 16 shows an example of the C source code 1511. This C source codeis written in C language and is input into the present compiler. The Csource program shown in FIG. 16 is the same as that shown in FIG. 4A andtherefore is not described here.

The intermediate code generation means 1501 converts the C source code1511 and generates the first intermediate code 1512. This conversion isthe same as that performed by a conventional compiler and therefore isnot described.

FIG. 17 shows the first intermediate code 1512. The first intermediatecode 1512 shown in FIG. 17 is the same as that shown in FIG. 5A andtherefore is not described here.

In this embodiment, the present compiler generates the firstintermediate code 1512 shown in FIG. 17 from the C source code 1511shown in FIG. 16.

The object code detection means 1502 detects instruction sequences whosepredetermined operations are executed when their predeterminedconditions are satisfied.

The conditional instruction conversion means 1503 converts a sequence ofinstructions detected by the object code detection means 1502 intoconditional instructions and generates the second intermediate code 1513from the first intermediate code 1512. The object code detection means1502 and the conditional instruction conversion means 1503 are describedin more detail later.

FIG. 18 shows the second intermediate code 1513.

In FIG. 18, the intermediate code “a cmpeq b” 1801 is a conditionalcomparison code for comparing the variables “a” and “b”. When thevariables are equal, an operation flag is set, and when the variablesare not equal, the operation flag is reset. The intermediate code “c=0”1802 is a code for transferring the immediate “0” to the variable “c”.The intermediate code “c=:true 1” 1803 is a code which is executed whenits condition is satisfied. With this intermediate code 1803, theimmediate “1” is transferred to the variable “c”, only when thecondition included in the preceding comparison code is satisfied (whenthe operation flag is set). The intermediate code 1304 is a code forcalling the function “f”.

In this embodiment, the present compiler generates the secondintermediate code 1513 shown in FIG. 18 from the first intermediate code1512 shown in FIG. 17.

The intermediate code optimization means 1504 optimizes the secondintermediate code 1513 and generates the intermediate code 1514. Thisoptimization is the same as that performed by a conventional compilerand therefore is not described here.

In this embodiment, when receiving the second intermediate code 1513shown in FIG. 18, the intermediate code optimization means 1504 does notperform the optimization processing. This is because the input secondintermediate code does not include codes to be optimized. Therefore, thethird intermediate code 1514 is the same as the second intermediate code1513 shown in FIG. 18.

The machine instruction generation means 1505 converts the thirdintermediate code 1514 and generates the machine instruction 1515. Thisconversion is the same as that performed by a conventional compiler andtherefore is not described here.

FIG. 19 shows the machine instruction 1515.

In FIG. 19, the machine instruction “cmpeq r0, r1” 1901 is a conditionalcomparison instruction for comparing values of the registers “r0” and“r1”. When the values are equal, the operation flag is set; when thevalues are not equal, the operation flag is reset. The machineinstruction “mov 0, r2” 1902 is a transfer instruction for transferringthe immediate “0” to the register “r2”. The machine instruction “movt 1,r2” 1903 is an instruction which is executed when its condition issatisfied. With this machine instruction 1903, only when the conditionis satisfied by the result of a comparison instruction (when theoperation flag is set); the immediate “1” is transferred to the register“r2”. The machine instruction 1904 is an instruction for calling thefunction “f”.

In this embodiment, the present compiler generates the machineinstruction 1515 shown in FIG. 19 from the third intermediate code 1514shown in FIG. 18.

FIG. 20 is a flowchart showing the operation of the object codedetection means 1502 and the conditional instruction conversion means1503 of the present compiler.

The following is a description of the object code detection means 1502and the conditional instruction conversion means 1503 of the presentcompiler to which the first intermediate code 1512 shown in FIG. 17 isinput, with reference to FIG. 17.

(1) The first intermediate code is input into the object code detectionmeans 1502 and the conditional instruction conversion means 1503, andthe initial value “1” is assigned to the variable n (step S2001). Inthis example, the first intermediate code shown in FIG. 17 is obtained.

(2) The compiler judges whether the n^(th) intermediate code indicates acomparison (step S2002). This process is repeated by incrementing n byone until the judgement result becomes “Yes” (in this repetition, thejudgement result in step S2002 is No, the process proceeds to stepS2011, and the judgement result in step S2016 is Yes). In this example,the 1st intermediate code of the first intermediate code indicates acomparison so that, when n is 1, the judgement result in step S2002becomes Yes and the process proceeds to the judgement in step S2003.

(3) The compiler judges whether the n+1^(th) intermediate code indicatesa conditional branch and whether its branch destination is the n+4^(th)intermediate code (step S2003). When the judgement result is No, n isincremented by one and the process returns to step S2002 to find anintermediate code indicating a comparison (in this case, the judgementresult in step S2003 is No, the process proceeds to steps S2011, and thejudgement result in S2016 is Yes). In this example, the 2nd intermediatecode shown in FIG. 17 indicates a conditional branch whose branchdestination is the n+4^(th) intermediate code. Therefore, when n+1 is 2,the judgement result in step S2003 becomes Yes and the process proceedsto the judgement in step S2004.

(4) The compiler judges whether the n+2^(th) intermediate code indicatesa transfer (step S2004). When the judgement result is No, n isincremented by 2 and the process returns to step S2002 to find anintermediate code indicating a comparison (in this case, the judgementresult in step S2004 is No, the process proceeds to step S2012, and thejudgement result in step S2016 is Yes). In this example, the 3rdintermediate code shown in FIG. 17 indicates a transfer, so that whenn+2 is 3, the judgement result in step S2004 becomes Yes and the processproceeds to the judgement in step S2005.

(5) The compiler judges whether the n+3^(th) intermediate code indicatesan unconditional branch whose branch destination is the n+5^(th)intermediate code (step S2005) When the judgement result is No, n isincremented by 3 and the process returns to step S2002 to find anintermediate code indicating a comparison (in this case, the judgementresult in step S2405 is No, the process proceeds to step S2013, and thejudgement result in step S2016 is Yes). In this example, the 4thintermediate code shown in FIG. 17 indicates an unconditional branchwhose branch destination is the n+5^(th) intermediate code. Therefore,when n+3 is 4, the judgement result in step S2005 becomes Yes and theprocess proceeds to the judgement in step S2006.

(6) The compiler judges whether the n+4^(th) intermediate code indicatesa transfer to the same variable of the n+2^(th) intermediate code (stepS2006). When the judgement result is No, n is increased by 4 and theprocess returns to step S2002 to find an intermediate code indicating acomparison (in this case, the judgement result in step S2006 is No, theprocess proceeds to step S2014, and the judgement result in step S2016is Yes). In this example, the 5th intermediate code indicates a transferto the same variable as the 3rd intermediate code, so that when n+4 is5, the judgement result in step S2005 becomes Yes and the processproceeds to the conversion process in step S2006.

(7) The n^(th) intermediate code indicating a comparison is changed intoa conditional comparison code specifying the same condition as the n+1intermediate code indicating a conditional branch (step S2007).

(8) The n+1 intermediate code indicating a conditional branch is deleted(step S2008).

(9) The n+3^(th) intermediate code indicating an unconditional branch isdeleted (step S2009).

(10) The n+4^(th) intermediate code indicating a transfer is changedinto a code which is executed when its condition is satisfied (stepS2010).

(11) N is increased by 5 and the compiler judges whether there is anyother intermediate code to be processed (steps S2015 and S2016). If so,the process in steps S2002-S2016 is repeated. In this example, thesecond intermediate code sequence 1513 shown in FIG. 18 is generated.

(12) The conditional instruction conversion means 1503 outputs thesecond intermediate code (step S2017).

In this manner, the present compiler generates conditional comparisoncodes and codes which are executed when their conditions are satisfied.The present processor can execute these codes.

Embodiment 5

The processor of Embodiment 5 decodes and executes the comparisoninstructions, the conditional addition instruction, the conditionaltransfer instruction, and the conditional branch instruction shown inFIG. 14, as the processor of Embodiment 4.

The present processor includes the same components as the processor ofEmbodiment 4 shown in FIG. 15.

The following description concerns only the differences between thepresent embodiment and Embodiment 4.

FIG. 21 shows the first intermediate code 1512. The first intermediatecode 1512 shown in FIG. 21 is the same as that shown in FIG. 6A andtherefore is not described here.

The intermediate code generation means 1501 generates the firstintermediate code 1512 shown in FIG. 21 from the C source code 1511shown in FIG. 16. This conversion is the same as that performed by aconventional compiler for generating conditional transfer instructionsand therefore is not described here.

The object code detection means 1502 and the conditional instructionconversion means 1503 generate the second intermediate code 1513 shownin FIG. 18 from the first intermediate code 1512 shown in FIG. 21.

FIG. 22 is a flowchart showing the operation of the object codedetection means 1502 and the conditional instruction conversion means1503 of the present embodiment.

The following is a description of the processing of the object codedetection means 1502 and the conditional instruction conversion means1503 of the present compiler to which the first intermediate code 1512shown in FIG. 21 is input, with reference to FIG. 21.

(1) The first intermediate code is input into the object code detectionmeans 1502 and the conditional instruction conversion means 1503, andthe initial value “1” is assigned to the variable n (step S2201). Inthis example, the first intermediate code shown in FIG. 21 is obtained.

(2) The compiler judges whether the n^(th) intermediate code of thefirst intermediate code indicates a comparison (step S2202). Thisprocess is repeated by incrementing n by one until the judgement resultbecomes “Yes” (in this repetition, the judgement result in step S2202 isNo, the process proceeds to steps S2207, and the judgement result inS2210 is Yes). In this example, the 1st intermediate code of the firstintermediate code indicates a comparison, so that when n is 1, thejudgement result in step S2202 becomes Yes and the process proceeds tothe judgement in step S2203.

(3) The compiler judges whether the n+1^(th) intermediate code indicatesa transfer (step S2203). When the judgement result is No, n isincremented by one and the process returns to step S2202 to find anintermediate code indicating a comparison (in this case, the judgementresult in step S2203 is No, the process proceeds to step S2207, and thejudgement result in S2210 is Yes). In this example, the 2nd intermediatecode shown in FIG. 21 indicates a transfer, so that when n+1 is 2, thejudgement, result in step S2203 becomes Yes and the process proceeds tothe judgement in step S2204.

(4) The compiler judges whether the n+2^(th) intermediate code indicatesa conditional transfer to the same variable as the n+1^(th) intermediatecode (step S2204). When the judgement result is No, n is incremented by2 and the process returns to step S2202 to find an intermediate codeindicating a comparison (in this case, the judgement result in stepS2204 is No, the process proceeds to step S2208, and the judgementresult in 52210 is Yes). In this example, the 3rd intermediate codeshown in FIG. 21 indicates the conditional transfer to the same variableas the 2nd intermediate code. Therefore, when n+2 is 3, the judgementresult in step S2204 becomes Yes and the process proceeds to theconversion process in step S2205.

(5) The n^(th) intermediate code indicating a comparison is convertedinto a conditional comparison code specifying a condition in theexclusive relation with that specified by the n+2^(th) conditionaltransfer (step S2205).

(6) The n+2^(th) intermediate code indicating a conditional transfer isconverted into a code which is executed when its condition is satisfied(step S2206).

(7) N is incremented by 3 and the compiler judges whether there is anyother intermediate code to be processed (steps S2209 and S2210). If so,the process in steps S2202-S2210 is repeated. In this example, thesecond intermediate code 1513 shown in FIG. 18 is generated.

(8) The conditional instruction conversion means 1503 outputs the secondintermediate code (step S2211).

In this manner, the present compiler generates executable conditionalcomparison codes and codes which are executed when their conditions aresatisfied for the present processor.

Embodiment 6

The processor of Embodiment 6 decodes and executes the comparisoninstructions, the conditional addition instruction, the conditionaltransfer instruction, and the conditional branch instruction shown inFIG. 14, as the processors of Embodiments 4 and 5.

The compiler of Embodiment 6 includes the same components as those ofthe processor of Embodiment 4 or Embodiment 5 shown in FIG. 15.

The following description concerns only the difference between thepresent embodiment and Embodiment 4.

FIG. 23 shows the first intermediate code 1512.

In FIG. 23, the intermediate code 2301 is a code for comparing thevariables “a” and “b” and setting a flag to indicate the comparisonresult; the intermediate code 2302 is a code for transferring theimmediate “0” to the variable “c” when the variables “a” and “b” are notequal; the intermediate code 2303 is a code for transferring theimmediate “1” to the variable “c” when the variables “a” and “b” areequal; and the intermediate code 2304 is a code for calling the function“f”.

The intermediate code generation means 1501 generates the firstintermediate code 1512 shown in FIG. 23 from the C source code 1511shown in FIG. 16. This conversion is the same as that performed by aconventional compiler for generating conditional transfer instructionsand therefore is not described here.

The object code detection means 1502 and the conditional instructionconversion means 1503 generate the second intermediate code 1513 shownin FIG. 18 from the first intermediate code 1512 shown in FIG. 23.

FIG. 24 is a flowchart showing the operation of the object codedetection means 1502 and the conditional instruction conversion means1503 of the present processor.

The following is a description of the processing of the intermediatecode 1512 shown in FIG. 23 by the object code detection means 1502 andthe conditional instruction conversion means 1503 of the presentcompiler.

(1) The first intermediate code is input into the object code detectionmeans 1502 and the conditional instruction conversion means 1503, andthe initial value “1” is assigned to the variable n (step S2401). Inthis example, the first intermediate code shown in FIG. 23 is obtained.

(2) The compiler judges whether the n^(th) intermediate code of thefirst intermediate code indicates a comparison (step S2402). Thisprocess is repeated by incrementing n by one until the judgement resultbecomes Yes (in this repetition, the judgement result in step S2402 isNo, the process proceeds to step S2409, and the judgement result inS2412 is Yes). In this example, the 1st intermediate code of the firstintermediate code indicates a comparison, so that when n is 1, thejudgement result in step S2402 becomes Yes and the process proceeds tothe judgement in step S2403.

(3) The compiler judges whether the n+1^(th) intermediate code indicatesa conditional transfer (step S2403). When the judgement result is No, nis incremented by one and the process returns to step S2402 to find anintermediate code indicating a comparison (in this case, the judgementresult in step S2403 is No, the process proceeds to step S2409, and thejudgement result in S2412 is Yes). In this example, the 2nd intermediatecode shown in FIG. 23 indicates a conditional transfer, so that, whenn+1 is 2, the judgement result in step S2403 becomes Yes and the processproceeds to the judgement in step S2404.

(4) The compiler judges whether the n+2^(th) intermediate code indicatesa conditional transfer to the same variable as the n+1^(th) intermediatecode (step S2404). When the judgement result is No, n is incremented by2 and the process returns to step S2402 to find an intermediate codeindicating a comparison (in this case, the judgement result in stepS2404 is No, the process proceeds to step S2410, and the judgementresult in step S2412 is Yes). In this example, the 3rd intermediate codeshown in FIG. 23 indicates a conditional transfer to the same variableas the 2nd intermediate code. Therefore, when n+2 is 3, the judgementresult in step S2404 becomes Yes and the process proceeds to theconversion process in step S2405.

(5) The compiler judges whether the condition of the n+2^(th)intermediate code indicating a conditional transfer is in an exclusiverelation with the condition of the n+1^(th) intermediate code indicatinga conditional transfer (step S2405). When the judgement result is No, nis incremented by 2 and the process returns to step S2402 to find anintermediate code indicating a comparison (in this case, the judgementresult in step S2405 is No, the process proceeds to step S2410, and thejudgement result in step S2412 is Yes). In this example, the conditionof the 3rd intermediate code indicating a conditional transfer is in theexclusive relation with the condition of the 2nd intermediate codeindicating a conditional transfer. Therefore, when n+2 is 3, thejudgement result in step S2405 becomes Yes and the process proceeds tostep S2406.

(6) The n^(th) intermediate code indicating a comparison is convertedinto a conditional comparison code specifying the same condition as then+2^(th) intermediate code indicating a conditional transfer (stepS2406).

(7) The n+1^(th) intermediate code indicating a conditional transfer isconverted into a transfer code (step S2407).

(8) The n+2^(th) intermediate code indicating a conditional transfer isconverted into a code which is executed when its condition is satisfied(step S2408).

(9) N is incremented by 3 and the compiler judges whether there is anyother intermediate code to be processed (steps S2411 and S2412). If so,the process in steps S2402-S2412 is repeated. In this example, thesecond intermediate code 1513 shown in FIG. 18 is generated.

In this manner, the present compiler generates conditional comparisoncodes and codes which are executed when their conditions are satisfied.The present processor can execute these generated codes.

The processor and compiler of the present invention has been describedabove by means of the embodiments, although it should be obvious thatthe present invention is not limited to the examples described above.Further variations are described below.

(1) The compiler of the present invention converts immediate code notincluding conditional transfer code and intermediate code includingconditional transfer code which the processor of the present inventioncannot execute into intermediate code including conditional transfercode which the processor of the present invention can execute. However,the compiler of the present invention may convert a machine instructionsequence not including conditional transfer instructions and a machineinstruction sequence including conditional transfer instructions whichthe processor of the present invention cannot execute into a machineinstruction sequence including conditional transfer instructions whichthe processor of the present invention can execute.

(2) In the above embodiments, immediates are transferred by transferinstructions. However, the contents of registers or memory may betransferred.

(3) In the above embodiments, transfer instructions are converted intoconditional instructions and instructions which are executed when theirconditions are satisfied. However, arithmetic logical instructions maybe converted into these instructions. For instance, Embodiment 1 may beapplied to addition instructions and an instruction sequence includingconditional addition instructions may be generated.

FIG. 25 shows a list of conditional addition instructions which theprocessor of Embodiment 1 can execute. This list includes three types ofconditional addition instructions, which is to say, the conditionaladdition instructions 2501. The conditions 2502 are signs indicatingconditions specified by respective conditional addition instructions.When two operation objects “a” and “b” are compared by a comparisoninstruction, the condition of the “addeq” 2503 is that “a” and “b” areequal; the condition of the “addgt” 2504 is that “a” is greater than“b”; and the condition of the “addge” 2505 is that “a” is greater thanor equal to “b”. Each conditional addition instruction is executed whenits condition is satisfied.

FIG. 26 shows an example C source program written in C language.

FIG. 27 shows an intermediate code sequence not including conditionaladdition instructions generated from the C source program shown in FIG.26.

FIG. 28 shows an intermediate code sequence including a conditionaladdition instruction generated from the intermediate code sequence shownin FIG. 27.

FIG. 29 shows a machine instruction sequence generated from theintermediate code sequence shown in FIG. 28.

The compiler of this variation converts the program shown in FIG. 26into the intermediate code shown in FIG. 27, into the intermediate codeshown in FIG. 28, and into the instruction sequence including aconditional addition instruction shown in FIG. 29.

(4) In Embodiments 4-6, the conditions of conditional instructions andconditional branch instruction are that the conditional flag is set.However, the conditions may be that the conditional flag is reset.

1-28. (canceled)
 29. A processor for executing an instruction sequencegenerated by converting a program that is capable of being described bymutually exclusive first and second conditional instructions, so thatthe instruction sequence includes only the first conditional instructionout of the first and second conditional instructions, wherein theprocessor has only the first conditional instruction out of the firstand second conditional instructions.
 30. The processor of claim 29,wherein the first conditional instruction is a conditional transferinstruction.
 31. The processor of claim 29, wherein the firstconditional instruction is a conditional arithmetic instruction.
 32. Aprocessor for executing an instruction sequence generated by convertinga program that is capable of being described by mutually exclusive firstand second conditional instructions, so that the instruction sequenceincludes only the first conditional instruction out of the first andsecond conditional instructions, wherein the processor is operable todecode only the first conditional instruction out of the first andsecond conditional instructions.
 33. The processor of claim 32, whereinthe first conditional instruction is a conditional transfer instruction.34. The processor of claim 32, wherein the first conditional instructionis a conditional arithmetic instruction.
 35. A processor for executingan instruction sequence generated by converting a program that iscapable of being described by mutually exclusive first and secondconditional instructions, so that the instruction sequence includes onlythe first conditional instruction out of the first and secondconditional instructions, wherein the processor is operable to executeonly the first conditional instruction out of the first and secondconditional instructions.
 36. The processor of claim 35, wherein thefirst conditional instruction is a conditional transfer instruction. 37.The processor of claim 35, wherein the first conditional instruction isa conditional arithmetic instruction.
 38. A processor that executes aninstruction sequence, comprising: a decoding unit operable to decode aninstruction sequence generated by converting a program that is capableof being described by mutually exclusive first and second conditionallyinstructions, so that the instruction sequence includes only the firstconditional instruction out of the first and second conditionalinstructions; and an executing unit operable to execute the instructionsequence decoded by the decoding unit; wherein the decoding unit isoperable to decode only the first conditional instruction out of thefirst and second conditional instructions.
 39. An instruction conversionapparatus for converting a program that is capable of being described bymutually exclusive first and second conditional instructions into aninstruction sequence executable by a processor, wherein the instructionconversion apparatus, when only the first conditional instruction out ofthe first and second conditional instructions is decodable by theprocessor, interchanges (a) a condition of the second conditionalinstruction with a condition of the first conditional instruction, and(b) an instruction executed when the condition of the second conditionalinstruction is satisfied with an instruction executed when the conditionof the second conditional instruction is not satisfied.
 40. Aninstruction conversion apparatus, comprising: an intermediate codegenerating unit operable to generate an intermediate code sequence byconverting a program that is capable of being described by mutuallyexclusive first and second conditional instructions; a detecting unitoperable to detect, from the intermediate code sequence, (a) aconditional instruction that judges whether to execute one of a firstoperation and a second operation, (b) a first operation code thatexecutes an instruction when the judgment result of the conditionalinstruction is to execute the first operation, and (c) a secondoperation code that executes an instruction when the judgment result ofthe conditional instruction is to execute the second operation; and aninterchanging unit operable, when only the first conditional instructionout of the first and second conditional instruction is decodable by aprocessor, to interchange (a) the second conditional instruction withthe first conditional instruction, and (b) an operation of the firstoperation with an operation of the second operation.